Vertex EDA
An exploration of EDA workflow optimization: making design steps easier to inspect, repeat, and improve.
Projects / Selected explorations
These project pages start with the themes I’m working on. I’ll expand each with verified implementation details, artifacts, and results as the write-ups are ready.
An exploration of EDA workflow optimization: making design steps easier to inspect, repeat, and improve.
Hardware design work focused on translating a specification into a practical, testable FPGA implementation.
A study of frequency-domain analysis and finite impulse response filtering, from mathematical model to implementation.
Project write-ups
The sections below are structured as a home for case studies. Replace these starter summaries with the exact scope and evidence you want to publish.
01 / EDA · workflow
Case study in progressA project area centered on EDA optimization. A complete write-up can describe the design-flow problem, the tools and scripts involved, how changes were evaluated, and what was learned. Specific metrics and tool versions can be added once confirmed.
02 / Digital logic · FPGA
Case study in progressA place to document hardware architecture, RTL structure, verification strategy, and the FPGA platform used. The published case study should distinguish measured results from design goals.
03 / DSP · signal processing
Case study in progressAn exploration of spectral analysis and finite impulse response filters. Future notes can include the signal model, coefficient choices, fixed-point considerations, and comparisons against a reference implementation.