EDA · Workflow 01
Vertex EDA
An exploration of EDA workflow optimization: making design steps easier to inspect, repeat, and improve.
EDAAutomationDesign flow
Explore project EE · COLUMBIA UNIVERSITY · NYC
Engineering notebook / 001
Building at the intersection of hardware & ideas.
I’m Xingcan, an Electrical Engineering student at Columbia. I explore digital design, EDA workflows, and signal processing—and document what I learn along the way.
Curious by design
DESIGN_SPACE / XC •••
FOCUS_01
Digital design
FOCUS_02
EDA workflows
FOCUS_03
Signal processing
Selected work / 2024—26
Things I’m building.
A few engineering threads I’m exploring across EDA, programmable logic, and digital signal processing.
Digital design · FPGA 02
FPGA Systems
Hardware design work focused on translating a specification into a practical, testable FPGA implementation.
RTLFPGAVerification
Explore project DSP · Signal processing 03
FFT / FIR Laboratory
A study of frequency-domain analysis and finite impulse response filtering, from mathematical model to implementation.
FFTFIRDSP
Explore project A quick introduction
A curious engineer, learning in public.
My interests live where abstract ideas meet real systems: modeling a signal, describing hardware, then understanding how the pieces behave together.
More about me →01 / THINK
Start from the model
Make assumptions visible, then turn them into a design that can be examined.
02 / BUILD
Make ideas tangible
Work across code, circuits, and tools to see how theory meets implementation.
03 / MEASURE
Ask what changed
Use reproducible checks and clear evidence to understand a result.
04 / SHARE
Leave a useful trail
Write notes so the next person—and future me—can follow the reasoning.
Field notes / Latest writing
Ideas, in progress.
Technical walkthroughs and short notes from the things I’m learning.
5 min read
A Practical Way to Think About EDA Workflow Optimization
A framework for making an engineering design flow easier to inspect, reproduce, and improve—without starting from an unverified speedup claim.
EDAWorkflowReproducibility
6 min read
Thinking in Transactions: A Starting Point for FPGA Streaming Designs
A small mental model for describing stream interfaces, latency, and backpressure before writing RTL.
FPGARTLDigital Design
Keep exploring